1. Field of Invention
The present disclosure of invention relates to a thin film transistor (TFT) substrate, and more particularly, to a thin film transistor substrate such as may be used in flat panel display applications and is capable of providing improved image quality in an image display device by maintaining a substantially constant drain-to-gate feedback capacitance even in the presence of mask misalignment.
2. Description of Related Art
Generally, flat panel image display devices include a thin film transistor (TFT) array formed on a transparent substrate that has interconnect electrodes provided thereon. Such flat panel devices display a predetermined but changeable (i.e., moving) image by applying corresponding voltages to different electrodes of the substrate. Examples of the image display device may include liquid crystal displays (LCDs), electronic paper displays (EPDs), and the like.
The thin film transistor (TFT) substrate typically includes a plurality of gate lines, data lines, pixel electrodes, and the like interconnected with a distributed array of field effect transistors.
A typical thin film transistor is a three-terminal electronic element that has a control terminal (gate electrode) connected to one of the gate lines, an input terminal (source electrode) connected to one of the data lines, and an output terminal (drain electrode) connected to one of the pixel electrodes.
Slight misalignments of masking steps during mass production can lead to variances across the substrate of an overlapping area that is usually present between the gate electrode and the drain electrode of each respective pixel area. This overlap corresponds to a drain-to-gate parasitic capacitance that is sometimes referred to as a Miller capacitance. When a fast rising voltage pulse is applied between the gate and source of a TFT that has inherent Miller capacitance, a negative feedback voltage results (which feedback may also be called a kickback signal). If Miller capacitance varies between pixel areas in a liquid crystal panel due to mask misalignment, it can result in uneven response to similar gate pulsing signals due to the across-the-substrate differences in kickback voltages among the various pixels. Such uneven response can create undesirable visual artifacts. As such, in the presence of mask misalignment, it is desirable to find a way to nonetheless maintain consistent, across-the panel image quality.